1. Field of the Invention
This invention relates to the field of semiconductor devices, and more specifically, to a process for controlling the etch bias during the formation of trenches with sub-micron dimensions.
2. Background Information
As semiconductor devices shrink ever smaller, so must its circuitry (components) such as trenches, contacts, plugs, vias, and interconnect lines. For example, in the current generation of semiconductor devices, the density of the circuitry (components) have become so compact that the dimensions of these components have decreased below submicron dimensions (.ltoreq.1 micron).
A consequence of the smaller devices and the increasing density of the components on these devices is that it becomes increasingly more important to control the critical dimensions of these components. As the dimensions for these components become even smaller and spaced relatively closer, for example, less than 0.5 micron (&lt;0.5.mu.) and even less than 0.25 micron (&lt;0.25.mu.), the processes used to make such components become less reliable and are unable to control the critical dimensions (CDs) of such components. If the critical dimensions of such components are not controlled, some of the components may be shorted together and consequently the semiconductor device being fabricated may not function properly.
In order to control the critical dimensions of these components, the processes used to manufacture these components should have good etch selectivity (to photoresists, metals, etc.) and exhibit good control over the etch bias. Prior art processes have the ability to control the critical dimensions within acceptable tolerance ranges for components with dimensions greater than approximately 1 micron (&gt;1.mu.). However, as the dimensions decrease below this level, i.e. at or below 1.mu., these processes do not provide sufficient control over the critical dimensions due to poor etch selectivity and etch bias control.
Etch selectivity is the ratio of the etch rates of different materials. For example, the etch selectivity for forming a trench may be the ratio of the etch rate of an silicon layer to a nitride layer (silicon: nitride). Etch bias is the difference between what is printed and what is actually formed after etching. For example, a photoresist prints a 1.0.mu. trench, but after etching a 1.25.mu. trench is actually formed, this is an example of a positive etch bias. Thus, a process with poor etch bias control may not be able to maintain the requisite critical dimensions for current and/or future generations of semiconductor devices.
FIGS. 1a-1c illustrate the generic or well known process steps for photolithographic and masking techniques used to form trenches. It should be noted that the figures are merely illustrative and have been simplified for clarity purposes and that similar processes may be used to form more complex structures. FIG. 1a illustrates a substrate 100 with an oxide layer 110 and a polish stop layer (or an etch hard mask layer) 120 deposited thereon. In FIG. 1b, a photoresist layer 130 has been spun above polish stop layer (or an etch hard mask layer) 120 and is exposed to light through mask layer 140. After photoresist layer 130 has been exposed to light, mask layer 140 is removed and photoresist layer 130 is developed in a developing solution to remove the portions of the photoresist layer 130 that were exposed to light. FIG. 1c illustrates photoresist layer 130 after the soluble portions of photoresist layer 130 have been removed. It should be noted that, although the above description describes positive resist techniques, it will be obvious to one with ordinary skill in the art, that negative resist techniques may also be used to pattern trenches.
Once the soluble portions of photoresist layer 130 have been removed, polish stop layer (or etch hard mask layer) 120, oxide layer 110, and substrate 100 are etched to form an opening 150, in order to create a trench. The particular etch chemistry and process parameters used, not only determine the amount of control over the critical dimensions, such as width and length, but also control the etch selectivity (to photoresists, metals, etc.) and the etch bias when forming a trench.
As illustrated in FIG. 1d, prior art processes are unable to control the critical dimensions of opening 150. The sidewalls of opening 150, as shown in FIG. 1d are not vertical and slope outward at the top of the opening. This is due in large part to poor etch selectivity and poor etch bias control. Photoresist layer 130 is removed after the formation of opening 150, however, it is illustrated in FIG. 1d by a dashed line to illustrate the difference between the printed CD and the resultant CD. As shown in FIG. 1d, because the resultant trench (i.e. opening 150) is larger than the pattern printed by photoresist layer 130 there is a positive etch bias. For packing densities and electrical integrity, it is ideal to be able to control the etch bias in order to keep the final CD the same as the printed CD. However, typical prior art etch processes only have the ability to form trenches that have a positive etch bias.
Since prior art processes typically form trenches with a positive etch bias, there is a greater importance placed upon the photolithography process which prints the desired critical dimensions. In other words, prior art processes print at smaller dimensions than the desired critical dimensions. For example, if a trench formation process exhibits a positive etch bias of approximately 0.05.mu., then in order to get a 0.25.mu. trench, the lithography method must print at approximately 0.2.mu.. However, as dimensions start to shrink the lithography processes are very limited in how small the dimensions can be printed. Thus, if the trench formation process had good etch bias control, one could print at or about the same size/dimensions of the critical dimension desired.
Another problem with prior art trench processes is that the type of etch chemistries which are used in order to have a manufacturable process form a buildup in the etching chamber. After etching several wafers the chamber becomes dirty due to this buildup and must be cleaned before manufacturing can continue. Thus, the faster the chamber gets dirty the more the manufacturing process is slowed down, which means fewer wafers are processed in a greater amount of time.
Thus what is needed is a method for forming trenches with improved etch selectivity and improved etch bias control such that smaller and more dense semiconductor devices may be fabricated and still exhibit good electrical performance. It is also preferable that this method improves the throughput of the fabrication process by increasing the time between etch chamber cleaning.